Reference is now made to FIG. 1 showing a block diagram of an n-bit Johnson counter circuit 10. The counter circuit 10 includes n flip-flops 12(l)-12(n) arranged in cascade with the output of one flip flop 12 coupled to the data input of a next flip flop. The output of the last flip-flop 12(n) is fed back to the data input of the first flip-flop 12(l) with a signal inversion. The clock inputs (>) of each of the included flip-flops 12 are coupled to receive a common clock signal (CLK). The output bits Q1-Qn of the counter circuit 10 are taken at the corresponding outputs of the included flip-flops 12. In an embodiment, the flip-flops 12 comprise D-type flip-flops as well known to those skilled in the art. Each D-type flip-flop 12 includes a data input D and a pair of complementary data outputs Q and QB. The Q output of one flip-flop is coupled to the data input D of the succeeding flip flop, and the QB output of the last flip-flop is coupled to the data input D of the first flip-flop (thus implementing the data inversion, which could instead be implemented using a logic inverter connected to the Q output). The counter circuit 10 functions as divider of the clock signal CLK to produce n output clock signals Q1-Qn, with each output clock signal having a frequency equal to the clock signal frequency divided by 2n and being phase shifted relative to each other by the period of the clock signal. See, FIG. 1A for output waveforms for an n=4 Johnson counter.
Reference is now made to FIG. 2 showing a block diagram of an m-bit ripple counter circuit 20. The counter circuit 20 includes m flip-flops 22(l)-22(m) arranged in cascade with the data output of one flip flop 12 coupled to the clock input (>) of a next flip flop. More specifically, the output of a previous flip-flop 22 is coupled to the clock input of a succeeding flip-flop. A complementary data output of each flip-flop 22 is coupled to the data input D of that same flip-flop. The first flip-flop 22 is coupled to receive an input clock signal CLK at its clock input. The output bits Q1-Qm of the counter circuit 20 are taken at the corresponding data outputs of the included flip-flops 22. In an embodiment, the flip-flops 22 comprise D-type flip-flops as well known to those skilled in the art. Each D-type flip-flop 22 includes a data input D and a pair of complementary data outputs Q and QB. The Q output of one flip-flop is coupled to the clock input of the succeeding flip flop, and the QB output of each flip-flop is coupled to the data input D of that same flip-flop (alternatively, an inverter circuit may be coupled to the Q output to provide the inverted feedback to the data input). The counter circuit 20 functions as divider of the clock signal CLK to produce n output clock signals Q1-Qn, with each output clock signal having a frequency equal to one half of the signal received at its clock input. See, FIG. 2A for output waveforms for m=4.
There is a need for an improved counter circuit operable at a reduced power consumption.